This invention relates to processes for formation of vias used for interconnecting metal layers of a multilevel metallization structure employed in integrated circuits.
Integrated circuits are becoming increasingly fast, and correspondingly, devices and feature sizes are shrinking. This allows for much higher device packing density on chips, and consequently lower cost per device.
When devices were relatively large, one layer of metal was adequate to provide all of the metal interconnections and other wiring needed to build a complete integrated circuit, without wiring requirements limiting device packing density. To avoid such a limitation as device dimensions have shrunk, it has become necessary to develop multilevel metallization schemes and to reduce certain metal dimensions.
In a single level metallization system, contact is made to the underlying silicon devices through contact holes etched through the dielectric separating the silicon from the interconnect metal. Multilevel metallization systems are comprised of alternating layers of dielectric and metal materials. The metal interconnects on the metal layer closest to the silicon surface (M1), make contact to the underlying silicon devices through contact holes, just as in single level systems. The successive metal layers, designated M1 to M(n), where n is the number of metal layers, are electrically connected to each other as required by appropriately located holes, referred to as vias, through the interlevel dielectric layers (ILD""s). The dielectric layer between the silicon surface and the first metal layer closest to the silicon is designated ILDO. Vias are typically filled with a conductor such as aluminum or tungsten. The conducting material filling the via is called a via plug.
Interconnect lines on each metal layer are separated by spaces. These spaces are filled with dielectric when the next dielectric layer is deposited. The width of one metal line plus one space is referred to as pitch. Many factors, including transistor size, circuit layout, and the number of metal layers that can be used, enter into the choice of the pitch for the different metal layers. The minimum pitch for M1 is usually set by the minimum transistor size and by lithography tolerances to insure that adjacent lines, at the minimum pitch, completely cover contacts without shorting to each other. After pitch is determined, the line and space dimensions are defined by circuit performance requirements such as RC time constants and reliability, as well as by the capability of the process to provide lines of minimum width. Minimum pitch for the M2 and M3 layers of metal are generally successively larger than for the M1 level, being determined by factors other than transistor size. If, however, vias are stacked one over another between successive metal layers, as is sometimes done to enhance performance and increase packing density, the pitches of all the layers contacted by the stacked via are generally maintained the same to facilitate layout.
Via dimensions are typically determined by the design current expected to flow through the via plug and by the resistance of the plug itself, as well as by variances and limitations imposed by lithography, etch, and via-fill processes. As device dimensions shrink and the line widths at the lower metallization levels such as M1 and M2 become correspondingly smaller, via cross sectional area decreases, and the via aspect ratio (AR), defined as via height/via width, tends to increase. The via aspect ratio is critical to the determination of how, and with what metal, the via is filled.
The generally preferred manufacturing method of filling vias having AR greater than 1 is Chemical Vapor Deposition of tungsten, (CVD tungsten process). Generally, the CVD tungsten process inherently provides better step coverage than competing processes such as sputtering of aluminum. It therefore is a better choice for uniformly coating the sides and bottoms of holes with high aspect ratio, thus yielding substantially void free plugs. Additionally, the CVD tungsten process is a manufacturing-proven process for filling high aspect ratio vias.
Two somewhat different CVD tungsten processes are in common use.
1. Selective Tungsten CVD, and
2. Blanket Tungsten CVD with Etchback or Chemical Mechanical Polishing (CMP).
Both are based on the chemical reduction of tungsten hexafluoride (WF6), a highly reactive gas. The process used for via fill between two metal layers is Blanket Tungsten CVD. In this process, tungsten hexafluoride is reduced by hydrogen in accordance with the reaction:
WF6+3H2+(heat)xe2x86x92W+6HF
The blanket tungsten process results in deposition of tungsten over the entire surface of the interlevel dielectric layer, and in filling of the vias over the underlying metal. The underlying metal is usually aluminum or an aluminum alloy, the preferred interconnect metal in most applications. In some applications, the entire tungsten layer deposited on the dielectric surface is subsequently etched back or polished using CMP, leaving only the plug in the via. In other applications the tungsten on the dielectric surface is patterned and used as interconnect metal. This may be accomplished by directly patterning the tungsten, or the ILD may have trenches patterned and etched before tungsten deposition. In this case, when excess tungsten is etched or polished off the surface, metal interconnect lines remain.
Before depositing the CVD tungsten, a thin barrier/nucleation/adhesion film is deposited on the dielectric surface and into the vias, coating the underlying aluminum with a protective barrier. This barrier prevents damaging interaction between the aluminum and the reactants and reaction products of the tungsten deposition. Preferred materials for the barrier/nucleation/adhesion film are TiN and TiW, with TiN being the most frequently used. A serious yield problem arises if, for any reason such as worst case tolerance buildup, misalignment of vias and the underlying metal result in vias not mating properly and extending outside of the underlying metal. This results in formation of trenches in the dielectric adjacent the metal lines during via overetch. The portion of the via extending beyond the metal can etch downward to the next lower metal layer or to the silicon in extreme cases, causing an interlevel short. Additionally, the trenches have high aspect ratio, and are difficult to completely fill with tungsten. Low density metal or actual metal voids in the trench regions can result, trapping gases therein and causing reliability problems. Finally, there is a high probability that the edge of the underlying aluminum interconnect metal, exposed due to the misalignment, will not be adequately protected by the barrier layer. This would result in a violent chemical reaction between the exposed aluminum and the WF6 and/or HF during deposition of the tungsten plug, causing severe damage to the structure. This phenomenon has been termed xe2x80x9cexploding viasxe2x80x9d.
To insure that interconnect metal and via plug make contact over the entire end surface of the plug and to reduce the occurrence of trench formation, exploding vias, and interlevel shorts, it has been common practice to provide for a minimum required border of metal around the via. This border or overlap is intended to account for any variations in metal and via dimensions and also for any misalignment tolerance of the lithography tool used. Borders are made sufficiently large to assure that vias do not extend beyond the underlying metal under worst case conditions of misalignment and/or dimensional tolerance buildup. If the metal line width is not adequate to provide the minimum required border, it is increased where it encounters a via, as shown in FIG. 2d. Since the minimum space can not decrease where the line width increases, the minimum pitch in this contacted case is greater than the non-contacted pitch previously described. This practice has the disadvantage of limiting the device packing density due to the increase in contacted metal pitch.
Design rules establishing the minimum size of borders around vias can be tightened; allowing smaller borders around vias if:
1. Tolerances associated with line, space, and pitch dimensions are reduced, and/or,
2. Tolerances associated with misalignment of vias caused by lithography are reduced.
While these steps will reduce the loss in device packing density caused by an increase in metal pitch due to widening of metal lines at vias, they do not fully compensate for that loss, and they also introduce added cost to the manufacturing process.
The use of borderless vias is attractive from a packing-density and manufacturing cost viewpoint, but all of the aforementioned problems associated with misalignment are magnified in this case. A method for solving the exploding via problem for borderless vias is described by the inventor in an earlier U.S. patent application Ser. No. 08/595,150 (B279), which is hereby incorporated by reference. According to this earlier method, a conformal protective insulating cap layer, silicon nitride or silicon oxynitride by way of example, is deposited over the metal line before ILD deposition. A two step directional via etch is utilized. The first portion of the etch has high selectivity, with high oxide etch rate compared with nitride etch rate. The nitride cap layer thereby acts as an etch stop on the top metal surface. Although for misaligned vias, a trench forms in the dielectric adjacent the metal lines during via overetch, the nitride on the metal sidewalls is substantially unaffected during via overetch due to the high selectivity. The second portion of the etch removes the nitride cap layer atop the metal lines, but due to its high directionality, leaves the sidewall cap layer substantially intact. The metal sidewalls are thus protected by the cap layer from WF6, thereby substantially eliminating the exploding via problem. The method as described above does not address the aforementioned problem of trench formation adjacent the metal lines, with the associated consequences of interlevel shorts and metal voids in the high aspect region.
A method for minimizing trench formation for slightly misaligned borderless vias is described by the inventor in U.S. patent application Ser. No. 08/601,541 (B077)U.S. Pat. No. 5,619,072, which is hereby incorporated by reference. According to this method, an insulating sidewall spacer is formed on the metal lines by deposition and etchback, before depositing the thick ILD and performing via etch. The sidewall spacer is comprised of an etch stop material relative to the oxide via etch, silicon nitride by way of example. For slightly misaligned vias, the portion of the via extending beyond the metal line falls above the spacers, and therefore during via overetch the etch stop material of the spacers prevents formation of a deep trench in that region, thereby lessening the probability of interlevel shorts. This method does not fully address the exploding via problem, since during etchback for sidewall spacer formation, the corner of the metal line may be exposed. This is true particularly since nitride is seen to be thinner at the metal corner, and nitride etch rate is experimentally observed to be enhanced near the corner. Additionally, the amount of misalignment tolerated by this process is limited to the thickness of the sidewall spacers, generally approximately 0.10-0.15 microns.
A single method which would substantially eliminate trench formation for slightly or moderately misaligned borderless vias and would additionally prevent exposure of metal sidewalls would provide a substantially complete solution to the problems of via etch-induced interlevel shorts and metal voids in the high aspect region, as well as preventing exploding vias.
I have provided an improved manufacturing process for forming via interconnects between metal layers in a multilevel metallization structure. This process substantially eliminates trench formation adjacent metal lines during via overetch, and prevents exploding vias, via metal voids in the trenches, and interlevel shorts caused by via overetch.
It is an object of this invention to provide an improved manufacturing process for fabricating multilevel metallization structures.
It is a further object to provide a manufacturing process which improves yield in the fabrication of multilevel metallization structures.
It is a further object to provide an integrated circuit with an improved multilevel metallization structure which permits higher device packing density on chips.
It is a further object to provide a manufacturing process which allows reducing the contacted pitch on metal layers of multilevel metallization structures.
It is a further object to provide a manufacturing process which permits the use of borderless vias in multilevel metallization structures.
It is a further object to provide a manufacturing process which permits loosening of the design rules that establish the minimum size of borders around vias in the fabrication of multilevel metallization structures.
It is a further object to provide a manufacturing process which substantially eliminates trench formation adjacent metal lines during via overetch.
It is a further object to provide a manufacturing process which substantially eliminates interlevel shorts between metal layers caused by via overetch.
It is a further object to provide a manufacturing process which substantially eliminates via metal voids adjacent metal lines, caused by via overetch.
It is a further object to provide a manufacturing process which substantially eliminates the problem of exploding vias in the fabrication of multilevel metallization structures.
It is a further object to provide a manufacturing process tolerant of misalignment of vias and underlying metal in the fabrication of multilevel metallization structures.